This invention relates to analog-to-digital conversion (ADC) and time-to-digital conversion (TDC) circuits.
Experimental High Energy and Nuclear Physics research depends heavily on the quality of measurement instrumentation. Better instrumentation enables better experimental results leading to advances in scientific knowledge. As the magnitude and complexity of these experiments continue to increase, the need for faster, more sensitive measurement electronics keeps growing.
Fast, low power, low noise, high sensitivity, and radiation resistant electronic instrumentation is essential for readout of particle detectors in experimental physics.
Detector readout instrumentation measures the timing, amplitude, integrated charge, and pulse shape of the detector response. Using a traditional readout method, the information content of low-level, fast signals from a detector is distorted by noise pick-up and crosstalk in analog transmission lines and by the amplifier noise. It is important to preserve the original signal quality. Conversion of the detector response into digital form also facilitates data acquisition and processing. Therefore, analog-to-digital conversion (ADC) and time-to-digital conversion (TDC) are two of the most important functions of detector instrumentation and, in particular, high energy physics detector instrumentation.
Applicants"" invention resides, in part, in an improved dual function superconducting digitizer circuit which can selectively function either as an analog-to-digital converter (ADC) or as a time-to-digital converter (TDC). Superconducting ADCs and TDCs can provide performance far superior to that obtained using conventional electronics by taking advantage of the intrinsic propertiesxe2x80x94high switching speed, quantum accuracy, dispersion-less transmission lines, radiation hardness, and extremely low power dissipationxe2x80x94of superconductivity. Since both ADC and TDC functions are desired in most measurement systems, a dual-function digitizer is not only more attractive from a system integration perspective but is also more marketable.
In circuits embodying the invention there is included a common selectable interface circuit coupled between the output of an ADC Front-End circuit and a digital counter and between the output of a TDC Front-End circuit and the same digital counter. The interface circuit includes switches to cause: a) in the ADC mode, the output of the ADC front-end to be applied to the counter input with little noise and cross talk and a periodic (or sampling) READ clock to be coupled to the READ/SAMPLING input of the digital counter; and b) in the TDC mode, a periodic reference clock to be applied to the counter input and an aperiodic HIT/EVENTS signal to be coupled via the interface to the READ/SAMPLING input of the digital counter.
An analog-to-digital converter (ADC) embodying the invention samples the analog input signal generated by a detector at specified time intervals and produces a digital output corresponding to the amplitude of the analog input signal. An ADC for use in practicing the invention includes a SQUID front-end. In response to a current pulse at the output of the detector, the SQUID front-end acts as a charge-to-flux converter and produces a stream of single flux quantum (SFQ) pulses. The number of SFQ pulses produced is proportional to the electrical charge (current) generated by the detector. The SFQ pulses are supplied to a counter by counting the number (N) of pulses over a specified time interval (sampling or integration time), a digital count is produced which is proportional to the charge in that time interval. Not only can the total charge be calculated by summing these counts, but the pulse shape can also be determined by using a fast sample rate. The major advantages of this ADC implementation are high sensitivity (4 nA/LSB at 100 Msamples/s, corresponding to produce a stream of output SFQ pulses at the first output when the input signal increases in one direction A time-to-digital converter (TDC) embodying the invention also includes a TDC based SQUID front-end and is based on counting the number of clock cycles between a xe2x80x9cstartxe2x80x9d event and a xe2x80x9cstopxe2x80x9d event. The resolution of the measurement is determined by a clock period. In the single hit case, a specified time trigger starts the TDC counter. Whenever a detector exceeds a specified threshold in a SQUID based front-end, a xe2x80x9chitxe2x80x9d is registered by producing an SFQ pulse. This hit pulse stops the counter, producing a digital output corresponding to the time interval between the trigger and the hit events. The ability to operate the counter at extremely high frequency ( greater than 30 GHz with present technology) enables the use of a clock with a very short time period (xcx9c30 ps). While a time resolution of 30 ps is already very attractive, it can be further improved by measuring finer time intervals (limited by timing jitter of the circuit, 2-3 ps) within a clock period. Another advantage of Applicants"" invention is that the same time resolution can be obtained in a multi-hit case. Each hit stops, resets, and restarts the counter. Therefore, when the next xe2x80x9chitxe2x80x9d event occurs, the TDC output corresponds to the time interval between two successive hits.
Each one of the ADC and the TDC includes a SQUID-based front-end and a digital counter. The digital counter may include an N-stage serial binary counter, a buffer memory coupled to the binary counter comprised of M rows, each having N stages for enabling serial to parallel conversion from the binary counter to the buffer memory, and an N-stage counter coupled to the mth row of the buffer memory for performing a parallel-to-serial conversion.
The nature of the counter input and the counting interval is different in the two cases. In the case of the ADC, the counter counts a stream of pulses of varying frequency generated by, and from, the ADC front-end. In the case of the TDC, it counts a periodic (constant frequency) pulse stream generated by a reference clock source. The counter readout occurs at regular intervals for the ADC determined by a sampling (readout) clock, while the counting interval for the TDC is xe2x80x9caperiodicxe2x80x9d since it depends on the occurrence of hits (start and stop triggers) at the TDC front-end. That is, for the ADC Counter there is periodic counting of an aperiodic stream of pulses and for the TDC Counter there is an aperiodic counting of periodic stream of pulses.
The ADC front-end, the TDC front-end, the selectable interface, the binary counter, and a multi-row memory buffer may be integrated on an IC chip which may also include a parallel-to-serial converter to the digital counter for a serial output version of the dual-function digitizer.
The IC chip may have two, or more, digitizer channels. Each channel can be used either as a TDC or as an ADC. Thus, with a single chip one can have a multi-channel high-sensitivity ADC, a multi-channel multi-hit TDC, or a combination of TDC and ADC channels.
Such flexibility is extremely important in high energy and nuclear physics instrumentation, allowing different measurements to be performed on the same setup. In accordance with Applicants"" invention, multiple copies of these digitizer pairs may be integrated on a single chip, and multiple chips may be integrated on a superconducting multi-chip module (MCM) to customize the instrument for each application.
Applicants"" invention thus includes a dual-function digitizer scheme, where the ADC and the TDC front-ends are connected to a common digital counter through a selectable interface. In accordance with the invention, an integrated circuit is formed that can selectively perform the functions of a sensitive analog-to-digital converter (ADC) as well as a high-resolution multi-hit time-to-digital converter (TDC).